The present invention relates to integrated circuits and, more particularly, to input structures for CMOS integrated circuits. A major objective of the present invention is to provide for gate-array integrated circuits with enhanced tolerance of electrostatic discharge (ESD).
Much of modern progress is associated with the increasing circuit density and speed of integrated circuits. CMOS (Complementary Metal-Oxide-Silicon) technology has provided integrated circuits with relatively low power requirements and, concomitantly, relatively low power dissipation. The low power dissipation minimizes damaging heat buildup, while low power requirements are attractive for portable applications and, more generally, for energy conservation.
In terms of both time and money, while the marginal per integrated circuit costs can be quite low (with reasonable manufacturing yields), the start up costs can be quite substantial. Thus, while integrated circuits can be very economical when produced in large quantities, low volume runs can be prohibitively expensive. Low volume runs are important, not only for certain specialized applications, but as intermediate steps in the development of integrated circuits eventually destined for large volume production.
An important sub-industry has emerged to provide for relatively low-cost, easy-to-design, "custom" integrated circuits. These custom circuits are widely referred to as "application-specific integrated circuits" or "ASICs". One of the earlier and still one of the most widely used type of ASIC is the CMOS gate array. A gate array "blank" is an integrated circuit "precursor" in which the circuit elements, e.g., transistors, are predefined, but most of the interconnections between circuit elements are not defined. Customization for specific applications is achieved by forming the interconnects.
Since several different integrated circuit designs can be based on the same gate-array blank design, the circuits can take advantage of the savings involved in the relatively high volume production of the blank. In addition, even the customization can take advantage of economies of scale, since the different custom designs require only different contact and metalization masks. Thus, gate arrays provide much of the cost savings associated with large volume runs to small volume ASIC runs.
One of the problems that CMOS gate arrays share with other integrated circuits, in particular, other CMOS integrated circuits, is vulnerability to ESD. While circuit design can comfortably limit the internal voltages of an integrated circuit design, there is little control over the voltages that can be applied to the inputs and outputs of the integrated circuit itself. Electric charges can build up in a number of situations; accumulated charges (static electricity) suddenly discharged across the pins of an integrated circuit can destroy the circuit. Those skilled in the art are aware of precautions that must be taken in system design and integrated circuit handling to minimize the occurrence of ESD. Nevertheless, ESD can and does occur. Therefore, it is highly desirable to reduce the vulnerability of the integrated circuits themselves to ESD.
Accordingly, it is general practice to include specific input/output structures, not only to buffer incoming and outgoing signals, but also to protect the circuit against ESD. Typical CMOS I/O buffers include at least one PMOS "pull-up" transistor and at least one NMOS "pull-down" transistor. The source of the PMOS transistor is connected to a logic high voltage (V.sub.DD), while the drain of the PMOS transistor is connected to the output and/or input voltage. The drain of the NMOS transistor is also connected to the input/output voltage and thus to the drain of the PMOS transistor. The source of the NMOS transistor is tied to a logic low voltage (V.sub.SS).
If the buffer is used for output, the gates of the PMOS and NMOS transistors are tied to internal transistors to implement a conventional pull-up/pull-down configuration. If the buffer is used for input only, the gate of the NMOS transistor is conventionally connected to the logic low voltage, while the gate of the PMOS transistor is connected to the logic high voltage. With their gates tied to fixed voltages, these input-only transistors do not serve the conventional pull-up/pull-down function actively. Herein, the PMOS and NMOS transistors of an input buffer are considered "inactive" pull-up and pull-down transistors, respectively.
Because ESD damage is associated with excessive current, more robust I/O buffers include several PMOS/NMOS pairs in parallel to divide ESD-induced currents. This design is referred to as "multi-finger", each of the transistor pairs constituting a "finger".
When a sufficiently great positive "first-breakdown" voltage (V.sub.t1) is applied to the drain of an NMOS pull-down transistor, an avalanche source/drain current is induced. The voltage drops to a snap-back voltage (V.sub.SB) as this current is established. At this point, the transistor functions as a NPN bipolar transistor, with current increasing with voltage. A further voltage increase to a second breakdown voltage (V.sub.t2), results in a further current surge and a concomitant voltage drop. This second voltage drop is associated with destruction of the transistor. The objective of ESD protection is to prevent transistors from suffering this second breakdown.
Due to processing non-uniformities, V.sub.t1 can vary among the different NMOS transistors of a multi-finger I/O buffer. During an ESD event, the voltage reduction after the first NMOS transistor enters its bipolar mode temporarily prevents other transistors from reaching their slightly higher V.sub.t1 s and thus from entering their bipolar modes. Thus, the first transistor must bear the entire current load.
If the first transistor reaches the second breakdown voltage V.sub.t2 before the other transistors enter their bipolar modes, the first transistor will be destroyed. The destruction can then cascade to other transistors. If other transistors enter bipolar mode before the first transistor reaches V.sub.t2, the resulting voltage drops and current divisions serve to protect all the transistors. Accordingly, it is desirable that all V.sub.t1 s be lower than all V.sub.t2 s for an I/O buffer. In other words, the nominal difference between V.sub.t2, and V.sub.t1 should be greater than the variations in V.sub.t1 and V.sub.t2 due to processing nonuniformities.
In the event of a negative-going ESD event, the drain/substrate junction is forward biased. The resulting current relaxes the charge buildup due to the ESD event. Thus, positive-going ESD events, during which the drain/substrate is reverse biased, are a greater concern than negative-going ESD events.
In theory, the PMOS pull-up transistors should act in a fashion complementary to the action of the NMOS pull-down transistors. It should counter charge build up during positive ESD events since its drain/substrate junction is forward biased. During negative ESD events, it should be subject to the two breakdown transitions at V.sub.t1 and V.sub.t2. However, in the response to the ESD event, the NMOS transistor dominates. This is due, in part, to the fact that the PMOS transistors are formed within an n-well within a p-type substrate. This renders them less efficient in their response to ESD events. Accordingly, the primary concern is the response of the NMOS transistors to positive ESD events. (In the atypical case where PMOS pull-up transistors act more efficiently than the NMOS pull-down transistors, negative ESD events are the primary concern.)
It has been observed empirically that input-only buffers are more subject to ESD destruction than are output buffers and input/output buffers. Thus, input buffers have become the weak link of ESD resistance. In accordance with this discovery, some input buffers connect each included NMOS gate to the drain of another NMOS transistor that has its gate and source tied to the logic low voltage. This arrangement has improved ESD protection.
The physical explanation for the success of this approach appears to be that the extra transistor lowers the voltage (V.sub.t1) at which the NMOS pull-down transistor transitions to bipolar operation relative to the voltage (V.sub.t2) at which the NMOS transistor in bipolar operation reaches second breakdown, and thus destruction. By lowering the voltage at which the transition to bipolar operation occurs relative to the voltage at which the transition to second breakdown occurs, one ensures that the other NMOS transistors will reach bipolar operation and share the ESD current before any of the transistors enter second breakdown.
The added transistors coupling the NMOS pull-down transistor gates to ground places the ESD protection afforded to input buffers on a par with that afforded to output-capable transistors. These additional transistors cost additional silicon real estate, which is particularly expensive in gate-array applications. What is needed is a more economical gate-array input buffer with enhanced ESD.